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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
FEATURES
* 6:1 single-ended multiplexer * Q nominal output impedance: 7 (VDDO = 3 .3V) * Maximum output frequency: 250MHz * Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V * Input skew: 225ps (maximum), VDD = VDDO = 3.3V * Part-to-part skew: 475ps (maximum), VDD = VDDO = 3.3V * Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS83056I is a low skew, 6:1, Single-ended Multiplexer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83056I has six selectable singleended clock inputs and one single-ended clock output. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. The device operates up to 250MHz and is packaged in a 16 TSSOP.
IC S
BLOCK DIAGRAM
CLK0 CLK1 CLK2 Q CLK3 CLK4 CLK5 SEL2 SEL1 SEL0 OE
PIN ASSIGNMENT
Q nc OE nc GND CLK5 SEL2 CLK4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO CLK0 SEL0 CLK1 VDD CLK2 SEL1 CLK3
ICS83056I
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
83056AGI
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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 4 6, 8, 9, 11, 13, 15 3 5 7, 10, 14 12 16 Name Q nc CLK5, CLK4, CLK3, CLK2, CLK1, CLK0 OE GND SEL2, SEL1, SEL0 VDD VDDO Type Output Unused Input Input Power Input Power Power Description Single-ended clock output. LVCMOS/LVTTL interface levels. No connect. Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Power supply ground. Clock select input. See Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. Core and input supply pin. Pullup Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) VDDO = 3.465V VDDO = 2.625V VDDO = 1.89V VDDO = 3.465V ROUT Output Impedance VDDO = 2.625V VDDO = 1.89V Test Conditions Minimum Typical 4 51 51 18 20 30 7 7 10 Maximum Units pF k k pF pF pF
TABLE 3. CONTROL INPUT FUNCTION TABLE
SEL2 0 0 0 0 1 1 1 1 Control Inputs SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 Input Selected to Q CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 LOW LOW
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REV. A JANUARY 18, 2006
Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 40 5 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 40 5 Units V V mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol V DD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 1.71 Typical 3. 3 1.8 Maximum 3.465 1.89 40 5 Units V V mA mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 35 5 Units V V mA mA
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO
83056AGI
Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
Test Conditions
Minimum 2.375 1.71
Typical 2. 5 1.8
Maximum 2.625 1.89 35 5
Units V V mA mA
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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK0:CLK5, SEL0:SEL2 OE CLK0:CLK5, SEL0:SEL2 OE Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDDO = 3.3V 5%; NOTE 1 VOH Output HighVoltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 5%; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VOL Output Low Voltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 5%; NOTE 1 -5 -150 2.6 1.8 VDD - 0.3 0.5 0.45 0.35 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 5 Units V V V V A A A A V V V V V V
Input High Current
IIL
Input Low Current
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) tR / tF odc Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle 20% to 80% 50 45 2.4 2.5 2. 7 2.7 55 Test Conditions Minimum Typical Maximum 250 3.0 2.9 22 5 475 50 0 55 Units MHz ns ns ps ps ps % dB
@ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
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REV. A JANUARY 18, 2006
Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) tR / tF odc Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle 20% to 80% 50 45 2.5 2.6 2.8 2.8 45 Test Conditions Minimum Typical Maximum 250 3.1 3.0 150 400 50 0 55 Units MHz ns ns ps ps ps % dB
@ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) tR / tF odc Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle 20% to 80% 100 45 2.7 2.8 3.2 3.3 50 Test Conditions Minimum Typical Maximum 250 3.8 3.8 150 475 700 55 Units MHz ns ns ps ps ps % dB
@ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
83056AGI
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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) tR / tF odc Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle 20% to 80% 100 40 2.5 2.5 3.0 2.9 60 Test Conditions Minimum Typical Maximum 250 3.5 3.4 17 5 300 500 60 Units MHz ns ns ps ps ps % dB
@ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V -0.2V, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) tR / tF odc Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle 20% to 80% 10 0 40 2.6 2.7 3.3 3.3 50 Test Conditions Minimum Typical Maximum 250 4.0 4.0 150 325 70 0 60 Units MHz ns ns ps ps ps % dB
@ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
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REV. A JANUARY 18, 2006
Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V5%
1.25V5%
2.45%
0.9V5%
V DD VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.25V5%
-0.9V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V5% 0.9V5%
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
V DD VDDO
SCOPE
Qx
Part 1 Qx
V
DDO
2
LVCMOS
GND
Part 2 Qy
V
DDO
2 tsk(pp)
-0.9V5%
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
83056AGI
PART-TO-PART SKEW
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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
VDD
80% 20% tR
80% 20% tF
CLK0:CLK5
2 VDDO
Q
2 tpLH
Clock Outputs
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
CLKx
V
DDO
Q
tPD1
Q t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
CLKy
Q
tPD2
tsk(i) = tPD2 - tPD1
INPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A JANUARY 18, 2006
Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83056I is: 874
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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX
FOR
16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
TABLE 8. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS83056AGI 83056AGI 16 Lead TSSOP tube -40C to 85C ICS83056AGIT 83056AGI 16 Lead TSSOP 2500 tape & reel -40C to 85C ICS83056AGILF 83056AIL 16 Lead "Lead-Free" TSSOP tube -40C to 85C ICS83056AGILFT 83056AIL 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83056AGI
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REV. A JANUARY 18, 2006
Integrated Circuit Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
REVISION HISTORY SHEET Rev A Table T8 Page 12 Description of Change Ordering Information Table - added Lead-Free marking. Date 1/18/06
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